CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

Andrei Pavlov, Manoj Sachdev - CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
Published: 2008-06-23 | ISBN: 1402083629 | PDF | 212 pages | 10.60 MB

As technology scales into nano-meter quarter, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and manifold defect mechanisms contribute to the increasing reach the ~ of of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays greaten the likelihood of cells with marginal steadiness and pose strict constraints on transistor parameters distributions.